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74ACT161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
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HIGH SPEED: fMAX =125 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 A (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 161 IMPROVED LATCH-UP IMMUNITY
B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT161B 74ACT161M Enable Input (LOAD), Count Enable Input (PE) and Count Enable Carry Input (TE), determine the mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides counting and parallel loading and sets all outputs on LOW state. A LOW signal on LOAD overrides counting and allows information on Parallel Data Qn inputs to be loaded into the flip-flops on the next rising edge of CLOCK. With LOAD and CLEAR, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The ACT161 is a high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and 2 double-layer metal wiring C MOS technology. It is ideal for low power applications mantaining high speed operation similar to eqivalent Bipolar Schottky TTL. It is a 4 bit binary counter with Asynchronous Clear. The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, Master Reset (CLEAR), Parallel PIN CONNECTION AND IEC LOGIC SYMBOLS
December 1998
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INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2 3, 4, 5, 6 7 10 9 14, 13, 12, 11 15 8 16 SYMBOL CLEAR CLOCK A, B, C, D PE TE LOAD QA to QD CARRY OUT GND VCC NAME AND FUNCT ION Master Reset Clock Input (LOW-to-HIGH, Edge- Triggered) Data Inputs Count Enable Input Count Enable Carry Input Parallel Enable Input Flip-Flop Outpus Terminal Count Output Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUT S CLEAR L H H H H H
NOTE:
O UT PUT S TE X X L X H X CL OCK X QA L A QB L B QC L C QD L D
FUNCT ION RESET TO "0" PRESET DATA NO COUNT NO COUNT COUNT NO COUNT
LOAD X L H H H X
PE X X X L H X
NO CHANGE NO CHANGE COUNT UP NO CHANGE
X:Don't Care A,B, C,D: Logic level of data input CARRY=TE * QA * QB * QC * QD
LOGIC DIAGRAMS
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TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 300 -65 to +150 300 Unit V V V mA mA mA mA
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ICC or IGND DC VCC or Ground Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -40 to +85 8 Unit V V V
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ns/V
1) VIN from 0.8 V to 2.0 V
DC SPECIFICATIONS
Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Low Level Output Voltage 4.5 5.5 4.5 5.5 II ICCT ICC IOLD IOHD Input Leakage Current Max ICC /Input Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 V I (* ) = V IH or V IL VO = 0.1 V or VCC - 0.1 V VO = 0.1 V or VCC - 0.1 V V I (* ) = V IH or V IL IO=-50 A IO=-50 A IO=-24 mA IO=-24 mA IO=50 A IO=50 mA IO=24 mA IO=24 mA VI = VCC or GND VI = VCC -2.1 V VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 0.6 4 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 Test Co nditions
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Valu e T A = 25 C Min. 2.0 2.0 T yp. 1.5 1.5 1.5 1.5 4.49 5.49 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1 1.5 40 75 -75 Max. -40 to 85 C Min. 2.0 2.0 0.8 0.8 Max.
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V V V
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A mA A mA mA
1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 . (*) All outputs loaded.
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL tPLH tPHL tPLH tPHL tPHL twL tw tw ts th ts th ts th tREM fMAX Propagation Delay Time CK to Q Propagation Delay Time CK to CARRY OUT Propagation Delay Time TE to CARRY OUT Propagation Delay Time CLEAR to CARRY OUT CLR pulse Width, LOW CK pulse Width (LOAD) HIGH or LOW CK pulse Width (COUNT) HIGH or LOW Setup Time HIGH or LOW (INPUT to CK) Hold Time HIGH or LOW (INPUT to CK) Setup Time HIGH or LOW (LOAD to CK) Hold Time HIGH or LOW (LOAD to CK) Setup Time HIGH or LOW (PE or TE to CK) Hold Time HIGH or LOW (PE or TE to CK) Recovery Time CLR to Q Maximum Clock Frequency 5.0(*) 5.0 5.0 5.0
(*)
T est Con ditio n
Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 1.5 5.5 9.5 10.5 1.5 1.5 1.5 7.0 5.5 6.0 2.5 2.0 2.0 1.5 -0.5 2.0 -2.0 1.5 -2.0 -0.5 115 125 11.0 8.5 10.0 3.0 3.0 3.0 9.5 0 8.5 -0.5 5.5 0 0.5 100 12.0 10.0 11.0 7.5 3.5 3.5 11.5 1.0 9.5 0 6.5 0.5 1.0
Un it
ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
(*)
(*)
5.0 5.0
(*) (*)
5.0(*) 5.0 5.0 5.0 5.0 5.0 5.0
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5.0 5.0
(*) (*)
(*) Voltage range is 5V 0.5V
CAPACITIVE CHARACTERISTICS
Symb ol Parameter V CC (V) C IN CPD Input Capacitance Power Dissipation Capacitance (note 1) 5.0 5.0 fIN = 10 MHz Test Co nditions Min. T yp. 4.5 45 Valu e T A = 25 oC Max. -40 to 85 o C Min. Max. pF pF Un it
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/n(per circuit)
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TEST CIRCUIT
CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500 orequivalent RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
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WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE (f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle)
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WAVEFORM 4: PROPAGATION DELAYS COUNTEABLE MODE (f=1MHz; 50% duty cycle)
WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle)
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Plastic DIP-16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
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SO-16 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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